1. Field
The following description relates to a DC-DC converter. The following description also relates to a DC-DC converter provided with a coupling network to dynamically manage load transient phenomena by facilitating detection of ripple information of the output voltage.
2. Description of Related Art
Many electronic devices use switching converters to generate voltages adjusted for use by differing components of the devices. A DC-DC converter is one type of such switching converters. For example, a DC-DC converter is widely used in various fields as a device to receive DC voltage, convert the received DC voltage into DC voltage at different level, and output that DC voltage at the different level.
A DC-DC converter may be controlled by using constant on-time (COT) technology. According to COT technology, one or more switches to generate output voltages (VOUT) turn on for a predetermined time interval during each switching cycle. Using COT technology can provide features such as relatively fast response time and simple circuit design.
Generally, a DC-DC converter has some loss resulting from resistance of the inductor, occurring when the DC-DC converter has a heavy load current. However, such loss usually does not greatly influence the operation of the DC-DC converter. For example, a greater proportion of loss is generated may be due to components outside the DC-DC converter chip such as a power switch, for example P-type metal-oxide-semiconductor (PMOS) or N-type metal-oxide-semiconductor (NMOS) or the inductor itself. In this situation, the loss generated due to currents consumed inside the chip of the DC-DC converter, that is, the proportion of the current inside the chip, is relatively low. Therefore, the DC-DC converter operates without difficulty, such as efficiency deterioration, at every frequency.
By contrast, a DC-DC converter that has a relatively lighter load current may have efficiency deterioration. When the load current is small, larger currents are consumed by the chip itself, compared to the load currents themselves. Accordingly, increasing currents inside the chip may cause deteriorated conversion efficiency of the DC-DC converter, because the currents inside the chip become more significant to overall conversion efficiency.
Hence, reducing the currents inside the chip may prevent the deteriorations in efficiency.
One way to reduce chip current consumption is to reduce the frequency of switching driving involved in chip driving. This approach is relevant because it is the driver related with switching driving that has the greatest influence on current use during chip driving. For example, when an arbitrary threshold value 5 mA is forcibly supplied while it is 1 mA at the output, the frequency of switching may be reduced by ⅕.
Another way to reduce chip current consumption is to apply a COT mode. According to this approach, the COT generator maintains constant on time during power switching driving. By using the COT technology, a comparator compares the feedback voltage with a reference voltage, and switches on the power switch for a predetermined time when the feedback voltage is lower than the reference voltage. Accordingly, the COT mode offers features not offered by an alternative control mode such as pulse-width modulation (PWM) mode when it comes to managing a load transient phenomenon that occurs when the load abruptly changes.
However, the COT mode has an aspect that it presents a greater ripple phenomenon than the PWM mode.
Because of the issues related to the greater ripple phenomenon, to the chip may rapidly detect the feedback output voltage in the COT mode. Without such a rapid determination, the chip is not able to adequately maintain the output voltage based on turn-on timing of the power switch. For example, the output voltage might otherwise be lower than the zero point defined by the reference voltage, which in turn causes the entire efficiency of the DC-DC converter to deteriorate.
A comparator may be provided, which may provide a high speed detection operation. However, it is difficult to produce high-speed design in consideration of appropriate gains for the comparator. Further, when a high-speed comparator is employed, the entire chip size increases, which also causes an additional issue related to increased current consumption.
Accordingly, yet another approach is to adjust the capacitance of the output capacitor which is connected to the output load. By using a capacitor with a larger equivalent series resistance (ESR), the feedback voltage as recognized at the comparator increases. It is thus easier to detect the feedback voltage.
However, depending on the situation, a capacitor with a relatively lower ESR is sometime used. When such a capacitor with a relatively lower ESR is used, it becomes relatively more difficult to detect the feedback voltage at the comparator provided in the DC-DC converter. In other words, it becomes more difficult to detect the ripple values of the output voltage.